1. Field of the Invention
The embodiments disclosed herein relate to circuits with built-in self-test architectures and, more particularly, to an asynchronous circuit with an at-speed built-in self-test (BIST) architecture.
2. Description of the Related Art
In data processing, a pipeline typically refers to an integrated circuit having multiple stages of logic blocks (i.e., multiple stages of combinational logic) that are connected in series so that the output of one stage (i.e., data-out) is the input of the next stage (i.e., data-in). A synchronous pipeline refers to a pipeline in which registers are inserted between the various stages and synchronously clocked to ensure that any data being transferred between stages is stable. That is, between each of the stages in a synchronous pipeline, a register is clocked so that the data-in to the logic block of a receiving stage is the final data-out from the logic block of the transmitting stage. An asynchronous pipeline refers to a pipeline that uses a handshaking protocol, rather clocked registers, to pass data from one stage to the next stage. That is, a transmitting stage performs its logic function (i.e., propagates data through its logic block) and also asserts a request signal to indicate to a receiving stage (i.e., the next stage in the pipeline) that new data is available for capture. Then, upon receipt of the request signal, the receiving stage captures this new data and asserts an acknowledge signal back to the transmitting stage to acknowledging receipt.
Asynchronous pipelines avoid a number of the problematic issues related to clocking (e.g., additional power requirements, management of clock skew, interfacing with environments clocked at different rates, etc.). However, today's methods of testing asynchronous pipelines or, for that matter, any other asynchronous circuits that rely on a handshaking protocol as opposed to synchronous clocking, require the circuit under test to be placed into a synchronous state in order to isolate timing faults (i.e., in order to isolate stuck-at and/or delay faults). Unfortunately, the cost, area and performance impacts associated with adding synchronous clocking to the circuit under test is relatively high, particularly in light of the fact that doing so inevitably changes the fail signature for the circuit under test and, thereby may mask a fail when the circuit is switched back to its asynchronous state.